1. Field of the Invention
The present invention relates to a standard cell and a semiconductor device.
2. Description of Related Art
An example of a standard cell used for semiconductor devices will be described. FIG. 1 is a plan perspective view to show a configuration example of a related standard cell. The standard cell shown in FIG. 1 is an inverter circuit, some wirings of which are omitted from the figure.
As shown in FIG. 1, the standard cell has a rectangular outer shape. The standard cell shown in FIG. 1 includes the following two regions. One is a Pch-Tr element region where a P channel Metal Oxide Semiconductor (MOS) transistor element (hereafter indicated by a Pch-Tr element) is formed. The other is an Nch-Tr element region where an N channel MOS transistor element (hereafter, indicated by an Nch-Tr element) is formed.
There are two Pch-Tr elements 21 and 22 provided in a region of N-well diffusion layer 10 to be turned into a Pch-Tr element region. There are also two Nch-Tr elements 31 and 32 provided in the Nch-Tr element region.
Pch-Tr element 21 includes gate electrode 211, drain electrode 212, and source electrode 215. Pch-Tr element 22 includes gate electrode 221, drain electrode 222, and source electrode 215. Pch-Tr elements 21 and 22 share the use of source electrode 215.
Nch-Tr element 31 includes gate electrode 311, source electrode 312, and drain electrode 315. Nch-Tr element 32 includes gate electrode 321, source electrode 322, and drain electrode 315. Nch-Tr elements 31 and 32 share the use of drain electrode 315.
FIG. 2A is a plan view of an active pattern of the standard cell shown in FIG. 1; FIG. 2B is a plan view of a gate pattern of the standard cell shown in FIG. 1; and FIG. 2C is a plan view of a wiring pattern of the standard cell shown in FIG. 1.
It is noted that in FIGS. 2A and 2C, the active pattern and the wiring are drawn by combining rectangular patterns as in the layout design, as a result of which, dividing lines are drawn in a pattern. Since the drawing on a mask used in the lithography process is performed without providing these dividing lines, the diving lines will not appear in the semiconductor device to be formed.
Active pattern 41 shown in FIG. 2A provides a generation region for source electrodes, drain electrodes, and channels of Pch-Tr elements 21 and 22. Active pattern 42 is provided along each side of the two long-sides and one of the short-sides of a rectangle, and in the inner edge thereof. Active pattern 42 provides an opening for applying a predetermined electric potential to N-well diffusion layer 10.
Active pattern 43 provides a generation region for source electrodes, drain electrodes, and channels of Nch-Tr elements 31 and 32. Active pattern 44 is provided along each side of the two long-sides and one of the short-sides of a rectangle, and in the inner edge thereof. Active pattern 44 provides an opening for applying an electric potential that is lower than that to N-well diffusion layer 10, to a P-well diffusion layer.
As shown in FIG. 2B, there are two kinds of dummy patterns provided in the gate pattern, besides gate electrodes of transistor elements. The first kind is a dummy pattern for the purpose of uniformly forming a pattern of gate electrodes at the time of gate-etching. Dummy patterns 25a, 25b, 27a, and 27b correspond to the pattern of this kind. By making the pattern of the gate electrode uniform, the gate length is made uniform, thereby suppressing variation in transistor characteristics.
As shown in FIG. 2B, each of dummy patterns 25a and 25b has an equal length to that of respective gate electrodes 211 and 221, and dummy patterns 25a and 25b are provided in parallel beside gate electrodes 211 and 221 respectively. Each of dummy patterns 27a and 27b has an equal length to that of respective gate electrodes 311 and 321, and dummy patterns 27a and 27b are provided in parallel beside gate electrodes 311 and 321 respectively. These dummy patterns 25a, 25b, 27a, and 27b are kept at a floating potential or fixed to a predetermined electric potential by being connected to the wiring. In this case, the electric potential of dummy patterns 25a, 25b, 27a, and 27b are kept at a floating state.
The second kind is a dummy pattern for the purpose of improving the planarization of an inter-layer insulation film to be formed on a gate pattern. Dummy patterns 26 and 28 correspond to the pattern of this kind. When an inter-layer insulation film formed on a gate pattern is planarized by CMP (Chemical and Mechanical Polishing) processing, a data rate, which is the proportion of the area occupied by the pattern in the gate-electrode forming layer, is preferably uniform in anywhere of the gate-electrode forming layer. Accordingly, it is necessary to increase the data rate of portions having a lower pattern density compared with the vicinity of a gate-electrode forming region, where the pattern density per unit area is relatively large. Specifically, the sizes of dummy patterns 26 and 28 are determined such that the pattern densities are within a predetermined range and dummy patterns 26 and 28 are provided as shown in FIGS. 1 and 2B.
Dummy patterns 26, 28 are kept at a floating potential or are fixed to a predetermined electric potential by being connected with the wiring. In this case, the electric potential of dummy pattern 26, 28 is fixed to a predetermined electric potential.
As shown in FIG. 2C, the wiring pattern includes wirings 51, 52, and 53. Although wiring 51 appears to be made up of a plurality of patterns, it is in reality made up of one pattern as described above. The same is also true with wiring 53.
Wiring 51 is connected with each of drain electrodes 212 and 222 and source electrode 215 of the Pch-Tr element, and active pattern 42 via well contact 61 as shown in FIGS. 1, 2A and 2C. Well contact 61 is a plug provided so as to pass through an inter-layer insulation film (not shown) and a gate oxide film (not shown) which are formed between the active pattern and the wiring pattern. Due to well contact 61, N-well diffusion layer 10 and drain electrodes 212 and 222 will have the same electric potential.
Wiring 53 is connected with each of source electrodes 312 and 322 and drain electrode 315 of the Nch-Tr element, and active pattern 43 via sub-contact 63 as shown in FIGS. 1, 2A and 2C. Sub-contact 63 is provided so as to pass through an inter-layer insulation film (not shown) and a gate oxide film (not shown) which are formed between the active pattern and the wiring pattern. Due to sub-contact 63, the P-well diffusion layer (not shown) and source electrode 312 and 322 will have the same electric potential.
It is noted that when the substrate on which the standard cell shown in FIG. 1 is formed is a P-type substrate, the P-well diffusion layer (not shown) and the substrate will have the same electric potential. Therefore, the contact plug which connects a P-well diffusion layer with a wiring pattern is referred to as sub-contact 63.
Contact 62 is a plug provided so as to pass through an inter-layer insulation film (not shown) formed between dummy pattern 26 and wiring 51 as shown in FIGS. 1, 2B, and 2C. Dummy pattern 26 will have the same electric potential as that of N-well diffusion layer 10. Moreover, contact 64 is a plug provided so as to pass through an inter-layer insulation film (not shown) formed between dummy pattern 28 and wiring 53. Dummy pattern 28 will have the same electric potential as that of the P-well diffusion layer (not shown).
As shown in FIGS. 1, 2A, and 2C, wiring 52 connects source electrode 215 of the Pch-Tr element with drain electrode 315 of the Nch-Tr element via well contact 61 and sub-contact 63.
Well contact 61, contacts 62 and 64, and sub-contact 63 are formed in the same process. The material for well contact 61, contacts 62 and 64, and sub-contact 63 is metal such as tungsten and copper, or a conductive material such as polysilicon doped with a conductive impurity.
Next, a standard cell including a resistance element will be described.
A DRAM (Dynamic Random Access Memory) is provided with a reference circuit for generating various reference voltages by resistive potential division. A reference circuit often utilizes resistance elements which are formed by diffusing a conductive impurity into a site from the surface to a predetermined depth of a substrate or well.
The configuration of a standard cell including a resistance element formed of a diffusion layer will be described. In this case, it is supposed that a MOS transistor is formed on the substrate as well.
FIG. 3A is a plan perspective view to show a configuration example of a standard cell including a resistance element; and FIG. 3B shows an equivalent circuit of the standard cell shown in FIG. 3A. FIG. 4 is a sectional view taken along line AB shown in FIG. 3A.
As shown in FIG. 4, a P-well diffusion layer is provided in each element-forming region of a resistance element and a MOS transistor, from the surface of P-type conductive substrate (simply referred to as “P-substrate”) 700 to a predetermined depth, and gate oxide film 710 is provided as an insulation film on the surface of P-substrate 700.
As shown in FIGS. 3A and 4, resistance element 500 is formed of a diffusion layer of an N-type conductive impurity and is formed in a region from the surface of P-well diffusion layer 600 to a predetermined depth. N-well diffusion layer 602 is formed in the surrounding of P-well diffusion layer 600, and the side face of P-well diffusion layer 600 is covered with N-well diffusion layer 602. FIG. 3A shows outer edge 622a and inner edge 622b of the pattern of N-well diffusion layer 602. Further, as shown in FIG. 4, deep N-well diffusion layer 604 is formed underneath P-well diffusion layer 600, and the bottom face of P-well diffusion layer 600 is covered with deep N-well diffusion layer 604.
Trench oxide film 551 is formed in the area that surrounds resistance element 500, and the side face of resistance element 500 is covered with trench oxide film 551. Dummy pattern 502 is provided above trench oxide film 551 in such a way as to surround the forming region of resistance element 500 along the planer pattern of trench oxide film 551. This dummy pattern 502 corresponds to the second of the two kinds of dummy patterns described above and is for the purpose of planarization by CMP processing. Dummy pattern 502 and the gate electrode (not shown) of the MOS transistor are in the same layer.
The reason why dummy pattern 502 is provided in the area that surrounds resistance element 500 is for the purpose of preventing the insulation film formed above the gate electrode from being ground faster than other sites thereby from being removed from the surface when it is ground by CMP processing. Dummy pattern 504 described later also has the same role as that of dummy pattern 502. The material of dummy patterns 502 and 504 is the same as that of the gate electrode (not shown), and in this case, they are made of a polysilicon layer into which a conductive impurity is diffused. Further, hereafter, the polysilicon layer into which a conductive impurity is diffused is simply referred to as a “polysilicon layer”.
Sub-contact diffusion layer 512 into which a P-type conductive impurity is diffused is formed outside trench oxide film 551. Since sub-contact diffusion layer 512 has a higher concentration of conductive impurities than that in P-well diffusion layer 600, it is indicated by “P+” in FIG. 4. The reason why sub-contact diffusion layer 512 has a higher concentration of conductive impurities is to decrease the contact resistance between the plug provided in the overlying layer and P-well diffusion layer 600. A diffusion layer for making contact with P-well diffusion layer 600, which has the same kind of conductive impurities as that of P-substrate 700, is referred to as a sub-contact diffusion layer.
On sub-contact diffusion layer 512, there is formed gate oxide film 710 which has a smaller film thickness than that of the trench oxide film formed next to each side of sub-contact diffusion layer 512. Because providing an opening through gate oxide film 710 will enable making contact with P-well diffusion layer 600 via sub-contact diffusion layer 512, the forming site of sub-contact diffusion layer 512 corresponds to the opening pattern of the present invention.
Trench oxide film 553 is formed in the area that surrounds sub-contact diffusion layer 512, and the side face of sub-contact diffusion layer 512 is covered with trench oxide film 553. Dummy pattern 504 is provided above trench oxide film 553 along the planar pattern of trench oxide film 553. Since the bottom face of trench oxide film 553 is at halfway point with respect to the depth of N-well diffusion layer 602, the side face of P-well diffusion layer 600 is covered with trench oxide film 553 and N-well diffusion layer 602.
Well-contact diffusion layer 514 into which an N-type conductive impurity is diffused is formed in the area that surrounds trench oxide film 553. Since well-contact diffusion layer 514 has a higher concentration of the conductive impurity than that of N-well diffusion layer 602, it is indicated by “N+” in FIG. 4. The reason why well-contact diffusion layer 514 has a higher concentration of the conductive impurities is to decrease contact resistance between the plug provided in the overlying layer and N-well diffusion layer 602. A diffusion layer for making contact with N-well diffusion layer 602 is referred to as a well-contact diffusion layer.
On well-contact diffusion layer 514, there is formed gate oxide film 710, which has a smaller film thickness than that of the trench oxide film formed next to each side of well-contact diffusion layer 514. Because providing an opening through gate oxide film 710 will enable making contact with N-well diffusion layer 602 via well-contact diffusion layer 514, the forming site of well-contact diffusion layer 514 corresponds to the opening pattern of the present invention.
Compared to resistance element 500 and well-contact diffusion layer 514 concerning the concentration of N-type conductive impurities, the concentration of N-type conductive impurities of resistance element 500 is lower than that of well-contact diffusion layer 514. Therefore, resistance element 500 is indicated by “N−” and well-contact diffusion layer 514 is indicated by “N+” in FIG. 4.
As shown in FIG. 3A, one of the two ends of resistance element 500 of a rectangular pattern is connected with tungsten wiring 533 via a contact, and the other end is connected with tungsten wiring 537 via a contact. Further, tungsten wiring 537 is connected with sub-contact diffusion layer 512 via sub-contact 522. Each of tungsten wiring 531 and tungsten wiring 535 is connected with well-contact diffusion layer 514 via well contact 524. Sub-contact 522 is a plug for connecting the wiring with sub-contact diffusion layer 512, and well contact 524 is a plug for connecting the wiring with well-contact diffusion layer 514.
The planar pattern of tungsten wiring 533 is rectangular. The planar pattern of tungsten wiring 537 has a shape in which a rectangular pattern and the planar pattern of sub-contact diffusion layer 512 are superposed with each other. However, in order to arrange that tungsten wiring 533 and tungsten wiring 537 in the same layer do not come into contact with each other, a part of the wiring pattern corresponding to the planar pattern of sub-contact diffusion layer 512 is removed as shown in FIG. 3A.
Tungsten wiring 531 and tungsten wiring 535, as shown in FIG. 3A, have a shape in which a portion which intersects with each of tungsten wiring 537 and tungsten wiring 533 is removed from the wiring pattern corresponding to the planar pattern of well-contact diffusion layer 514.
As shown in FIG. 4, insulation film 712 and insulation film 714 are stacked one after another on gate oxide film 710. Dummy pattern 502 and dummy pattern 504 are provided within insulation film 712 and on gate oxide film 710. Sub-contact 522 passes through gate oxide film 710 and insulation film 712 to reach sub-contact diffusion layer 512. Well contact 524 passes through gate oxide film 710 and insulation film 712 to reach well-contact diffusion layer 514. Tungsten wirings 531, 533, 535, and 537, which are in the same layer, are provided within insulation film 714 and on insulation film 712.
In order to make resistance element 500 insusceptible to noises from the substrate, deep N-well diffusion layer 604 is interposed between P-well diffusion layer 600, in which resistance element 500 is formed, and a P-well diffusion layer (not shown), in which another element (such as a transistor element in the vicinity) is formed, to separate respective P-well diffusion layers of resistance element 500 and another element. In this way, resistance element 500 is disposed on P-well diffusion layer 600 dedicated for its own element.
For the above described purpose, deep N-well diffusion layer 604 needs to be kept at a high-voltage potential so as to be reversely biased in the P-N direction with respect to P-well diffusion layer 600 without fail. N-well diffusion layer 602 is provided in order to supply a high-voltage potential to deep N-well diffusion layer 604, and well-contact diffusion layer 514 is provided to supply a high-voltage potential to N-well diffusion layer 602. A high-voltage is, for example, a power supply voltage (VDD). Hereafter, description will be made of the cases in which a VDD potential is applied. FIGS. 3A and 3B show wirings to which a VDD potential is applied. A VDD potential is applied to each of tungsten wirings 531, 533, and 535.
As so far described with reference to FIGS. 3A and 4, resistance element 500 is disposed in the center of the forming region of resistance element 500; sub-contact diffusion layer 512 for supplying an electric potential to P-well diffusion layer 600 is disposed around resistance element 500; and well-contact diffusion layer 514 for supplying an electric potential to N-well diffusion layer 602 and deep N-well diffusion layer 604 is disposed around sub-contact diffusion layer 512. Further, dummy pattern 502 is disposed between resistance element 500 and sub-contact diffusion layer 512; and dummy pattern 504 is disposed between sub-contact diffusion layer 512 and well-contact diffusion layer 514.
If a pattern made up of a polysilicon layer, such as dummy patterns 502 and 504, is not disposed in the area that surrounds resistance element 500 at all, the forming region of resistance element 500 will have an extremely low data rate of polysilicon layer compared with the region where a pattern of polysilicon layer is disposed. This will adversely affect the planarization by CMP processing. In order to avoid occurrence of the problem, dummy patterns 502 and 504 are disposed in the area that surrounds resistance element 500 so that the data rate of polysilicon layer in the forming region of resistance element 500 becomes closer to that in the forming region of a MOS transistor. Dummy patterns 502 and 504 are kept at a floating or VDD potential.
In recent years, as the degree of integration of semiconductor devices has increased, memory LSIs have larger storage capacity and system LSIs have more functions implemented, as a result of which the size of semiconductor devices has become larger. Moreover, improvements in signal processing speed have resulted in semiconductor devices having increased speeds. For semiconductor devices whose sizes steadily increase and which have higher speeds, the noise of power supply lines has become a problem. As a countermeasure, Japanese Patent Laid-Open No. 2006-253393 (hereinafter referred to as “Patent Document 1”) discloses an example of the method of suppressing the fluctuation of power supply voltage by providing a compensation capacity between power supplies having different electric potentials.
As a result of advances integration scale and processing speed, semiconductor devices utilize not only power supply voltages supplied from the outside, but also various internal power supply voltages which are produced by decreasing or increasing the power supply voltage supplied from the outside by means of an internal circuit. For that reason, a compensation capacity becomes necessary for each of those internal power supplies besides power supply voltages supplied from the outside. Although the compensation capacity is preferably provided in the free space of the chip, the necessary quantity of the compensation capacity may become very large, and the amount of free space in the chip may not be enough to provide the compensation capacity.
The above described reference circuit will be described by way of example. Since the reference circuit is made up of analog circuits, it is characteristically susceptible to noise. Taking into consideration the following two points: that the power supply voltage supplied to the reference circuit will be the original voltage to create a reference voltage in a chip; and that the reference circuit is susceptible to noise, it is particularly important that the reference circuit be disposed with a compensation capacity to control the power supply noise, and thus it becomes necessary to secure layout space for that.
Securing space for disposing compensation capacity in a chip will result in an increase in chip size. When compensation capacity is provided in the free space of a chip within a permissible range without increasing the chip size, countermeasure against the noise of the power supply lines may be insufficient and thus the noise may adversely affect circuit characteristics.
A decision must be made whether to give a higher priority to compensation capacity and to provide the necessary quantity of compensation capacity in a chip by increasing the chip size, or to give a higher priority to chip size and to provide a quantity of compensation capacity which can be disposed in the free space of the chip, but taking the risk that there will be an occurrence of noise from the power supply; however, solving one problem will result in a manifestation of the other problem.
Patent Document 1 discloses a technology of providing a compensation capacity in a circuit cell as a countermeasure against the problem that sufficient layout space for compensation capacity cannot be obtained. However, in the technology disclosed in the foregoing patent, it is considered to select the most important configuration from among a gate dummy pattern for compensation capacity, a well contact, and a sub-contact, depending on the purpose of the circuit cell, and the configuration selected is disposed in the circuit cell. Therefore, the object is not to dispose a gate dummy pattern for compensation capacity, a well contact, and a sub-contact all in a single cell.